VIP Control is Mutilating my Image!!!

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Looking from outside the FPGA, the hsync period is consistent during vblank and non-vblank.

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If this is also the case on the FPGA then I don't think you're seeing the issue that I was describing. If the vid_h_sync, vid_v_sync and vid_datavalid signals are consistent throughout the whole frame then there shouldn't be a problem using the 9.1 CVI.

The way to debug the problem is to look at the registers in the resolution_detection block within the CVI. The relevant HDL file is db/alt_vip_vid2is_resolution_detection.v. The registers that are of interest are:

next_active_sample_count[15:0] = next width

active_sample_count[16:1] = current width

active_sample_count[0] = current width valid

update_active_sample

The way they work is that for every cycle your vid_datavalid signal is high next_active_sample_count has 1 added to it. At the end of every active picture line update_active_sample goes high and next_active_sample_count is compared with active_sample_count. If they are different active_sample_count is updated. The active_sample_count register is what drives the control packet width (after it's gone through some clock synchronization registers into the control block).