VIP Control is Mutilating my Image!!!

Thanks for the info; I find timing issues to be far more scary than a few more ram blocks. I'll try 1/2 rate, and I'll reduce the bursting targets to 32.

I"ve just run a basic system that was generated on quartus 9.0sp2. It has CVI->Scaler->FB->CVO. There is nios2 control of the Scaler and it works fine! If I compare the SignalTap outputs from 9.1sp1 to the ones I've just made in 9.0sp2 I see that the former is reporting the pixel line length as 1273, and the latter is a perfect 1280. i now believe that even though 1273px are reported, 1280 are in fact being passed. this is causing elements downstream (mixer or cvo) to start a new line every 1273 pixels, but then a further 7 arrive before the real next line of pixels, causing a 7 pixels displacement for each successive line of pixels. Hence the 7 pixel skew.

I think there must be some significant changes to the CVI block in 9.1; it obviously doesn't like my input signals any more. But the scary thing is that they are completely vanilla - 1280x1024 60Hz with separate syncs! Nothing scary about that, hardly HD or anything exotic. My video decoder ASSP is the TI TVP7002, made by a bluechip company with a stellar reputation. I'd like to bring this to the attention of Altera, what is the best way to make a bug report?

I'll now add the rest of the blocks in the sopc and just get on with my application. I'll let you know if I re-introduce the bug. Thanks again for your help, I would be lost without it!