Honored Contributor
Honored ContributorHi Jakob,
Attached are some fresh screen grabs of my video signals. These are signals coming out of the FPGA though some spare pins that i have for TAP purposes. You'll see the calculated measurements of the signal on the grabs. There is a bit of jitter, about +/- 100ps which I think it good for a recovered clock. Given that my mean pixel clock is 108.9MHz, DE +ve period is 11.75us I should clock in 1279.6 pixels. The 0.4 pixels is acceptable error. I guess you are correct, seeing 1273 pixels in the control packet could be a symptom of a problem... I've also attached another SignalTap grab, this time coming out of the scaler (with control port attached). The final image on the LCD is exhibiting similar image distortion to that described above. The control packet reads: - width 1273 px - height 1024 lines - progressive It's the same as the control packet that I saw entering the scaler!? Also, the dout_valid signal is dipping a lot, does this look normal? Could all this come from having exceeded the fmax of the system? (TimingQuest says no) - is the scaler just not turning on?
