Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

VIP Clocked Video Output to LVDS

Dear community,

I wonder if anyone has used the Clocked Video Output from the VIP (Video IP Suite) together with an LVDS display. We think about using this IP with the ALTLVDS_TX. Unfortunately, I didn’t find a demo project or something else. Could you help out?

Best regards,

niosIIuser

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    The CVO will output the active video and blanking period, you only wanted to transmit video data? How about the V sync and H sync signals?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    CVO outputs DATA, VSYNC, HSYNC, DE and in general all the required signals for any use.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Yeah, so the LVDS serializer is only for video data.. I wonder how you wanted to transmit V sync and H sync signals.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    Yeah, so the LVDS serializer is only for video data.. I wonder how you wanted to transmit V sync and H sync signals.

    --- Quote End ---

    VSYNC and HSYNC (and usually DE) are embedded into the LVDS stream.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    I’m sorry for my late reply. As Socrates wrote it is pretty simple.

    IP-Component ALTLVDS_TX

    Number of channels: 3

    Deserialization factor: 7

    Output data rate: 497 Mbps

    Clock frequency: 71 MHz

    Phase alignment of “tx in”: 0 dgrees

    Register “tx_in” input port using: Checked, “tx_coreclock”

    Use “tx_outclock” output port: Checked

    Outclock divide factor: 7

    Phase alignment of “tx_outclock”: 0 degree

    A bit tricky was to assign the values in correct order, due to the fact that for most display the clock is in the “middle” of the packet. Therefore, it was necessary to rearrange the bits a little bit:

    wire  altlvds_tx_disp_tx_in;
    wire altlvds_tx_disp_tx_inclock;
    wire  altlvds_tx_disp_tx_out;
    wire altlvds_tx_disp_tx_outclock;
    assign altlvds_tx_disp_tx_inclock = vga_clk;
    assign altlvds_tx_disp_tx_in   = vga_r;
    assign altlvds_tx_disp_tx_in     = vga_g;
    assign altlvds_tx_disp_tx_in   = vga_r;
    assign altlvds_tx_disp_tx_in   = vga_g;
    assign altlvds_tx_disp_tx_in = vga_b;
    assign altlvds_tx_disp_tx_in = vga_g;
    assign altlvds_tx_disp_tx_in = vga_b;
    assign altlvds_tx_disp_tx_in    = vga_hs;
    assign altlvds_tx_disp_tx_in    = vga_vs;
    assign altlvds_tx_disp_tx_in    = vid_datavalid;
    assign altlvds_tx_disp_tx_in = vga_b;
    assign TXCLK = altlvds_tx_disp_tx_outclock;
    assign TXOUT0 = altlvds_tx_disp_tx_out;
    assign TXOUT1 = altlvds_tx_disp_tx_out;
    assign TXOUT2 = altlvds_tx_disp_tx_out;
    altlvds_tx_disp altlvds_tx_disp_inst (
      .tx_in       (altlvds_tx_disp_tx_in),
      .tx_inclock  (altlvds_tx_disp_tx_inclock),
      .tx_out      (altlvds_tx_disp_tx_out),
      .tx_outclock (altlvds_tx_disp_tx_outclock)
    );