Video Processing Problem

I am using Cyclone III Development Board and I want to take an input from computer via Bitec DVI receiver and directly pass it to monitor via Bitec DVI transmitter.

Here is the code, I used and I could not achieve what I want and have no idea why does it not work ?

Appriciate your answers

entity top is

port(

clk : in std_logic;

BITEC_DVI_IO_IN : in std_logic_vector(23 downto 0);

BITEC_DVI_IO_IN_DE : in std_logic;

BITEC_DVI_IO_IN_HSYNC : in std_logic;

BITEC_DVI_IO_IN_ODCK : in std_logic;

BITEC_DVI_IO_IN_VSYNC : in std_logic;

BITEC_DVI_IO_OUT_HSYNC : out std_logic;

BITEC_DVI_IO_OUT_DE : out std_logic;

BITEC_DVI_IO_OUT : out std_logic_Vector(23 downto 0);

BITEC_DVI_IO_OUT_VSYNC : out std_logic;

BITEC_DVI_IO_OUT_DVI_ISEL : out std_logic;

BITEC_DVI_IO_OUT_DVI_PD : out std_logic;

BITEC_DVI_IO_OUT_DVI_DKEN : out std_logic;

BITEC_DVI_IO_OUT_DVI_CTL1 : out std_logic;

BITEC_DVI_IO_OUT_DVI_CTL2 : 0ut std_logic;

BITEC_DVI_IO_OUT_DVI_CTL3 : out std_logic;

BITEC_DVI_IO_OUT_IDCKp : out std_logic;

BITEC_DVI_IO_OUT_IDCKn : out std_logic

);

end top;

architecture behavioral of top is

component vidout2

port (

is_clk : in std_logic := '0'; -- is_clk_rst.clk

rst : in std_logic := '0'; -- is_clk_rst_reset.reset

is_data : in std_logic_vector(23 downto 0) := (others => '0'); -- din.data

is_valid : in std_logic := '0'; -- .valid

is_ready : out std_logic; -- .ready

is_sop : in std_logic := '0'; -- .startofpacket

is_eop : in std_logic := '0'; -- .endofpacket

vid_clk : in std_logic := '0'; -- clocked_video.export

vid_data : out std_logic_vector(23 downto 0); -- .export

underflow : out std_logic; -- .export

vid_datavalid : out std_logic; -- .export

vid_v_sync : out std_logic; -- .export

vid_h_sync : out std_logic; -- .export

vid_f : out std_logic; -- .export

vid_h : out std_logic; -- .export

vid_v : out std_logic -- .export

);

end component;

component vidin

port (

is_clk : in std_logic := '0'; -- is_clk_rst.clk

rst : in std_logic := '0'; -- is_clk_rst_reset.reset

is_data : out std_logic_vector(23 downto 0); -- dout.data

is_valid : out std_logic; -- .valid

is_ready : in std_logic := '0'; -- .ready

is_sop : out std_logic; -- .startofpacket

is_eop : out std_logic; -- .endofpacket

vid_clk : in std_logic := '0'; -- clocked_video.export

vid_data : in std_logic_vector(23 downto 0) := (others => '0'); -- .export

overflow : out std_logic; -- .export

vid_datavalid : in std_logic := '0'; -- .export

vid_locked : in std_logic := '0'; -- .export

vid_v_sync : in std_logic := '0'; -- .export

vid_h_sync : in std_logic := '0'; -- .export

vid_f : in std_logic := '0' -- .export

);

end component;

signal locked :std_logic:='0';

signal c0,ready,valid,eop,sop,underflow,overflow,f,h,v: std_logic:='0';

signal data : std_logic_vector(23 downto 0):=(others=>'0');

begin

l2: vidin port map(clk,'0',data,valid,ready,sop,eop,BITEc_DVI_IO_IN_ODCK,BItEC_DVI_IO_IN,overflow,BITEC_DVI_IO_IN_DE,'1',BITEC_DVI_IO_IN_VSYNC,BITEC_DVI_IO_IN_HSYNC,f);

l3: vidout2 port map(clk,'0',data,valid,ready,sop,eop,BITEc_DVI_IO_IN_ODCK,BITEC_DVI_IO_OUT,underflow,BITEC_DVI_IO_OUT_DE,BITEC_DVI_IO_OUT_VSYNC,BITEC_DVI_IO_OUT_HSYNC,f,h,v);

BITEC_DVI_IO_OUT_IDCKp<=BITEC_DVI_IO_IN_ODCK;

BITEC_DVI_IO_OUT_DVI_ISEL<='1';

BITEC_DVI_IO_OUT_DVI_PD <='0';

BITEC_DVI_IO_OUT_DVI_DKEN <='0';

BITEC_DVI_IO_OUT_DVI_CTL1 <='0';

BITEC_DVI_IO_OUT_DVI_CTL2 <='0';

BITEC_DVI_IO_OUT_DVI_CTL3 <='0';

BITEC_DVI_IO_OUT_IDCKn <='0';

end behavioral;