Using UniPHY leaving RUP and RDN unconnected for a DDR2 SDRAM controller

I'm currently wading through this doc:

http://www.altera.com/literature/ug/ug_altoct.pdf

Looks like one might have to instantiate the control block, then set up a constraint to tell the tools to use that instantiated block..

UPDATE:

I managed to complete a compilation. I still need to test it but it got passed the OCT errors.

What I found - reading the uniphy docs for both ddr3 and qdr found here:

hhttp://www.altera.com/literature/lit-external-memory-interface.jsp?GSA_pos=6&WT.oss_r=1&WT.oss=uniphy%20qdr

The SOPC builder generated a tcl file per core:

uniphy_ddr3_0_pin_assignments.tcl

uniphy_qdrii_0_pin_assignments.tcl

and some readme.txt files.

What I had to do was run "Analysis ans Synthesis" first, then source these two files in the Quartus tcl console, then finish the compilation.

It sets up the constraints properly for the SOPC versions of these cores.

Since I prefer command line scripting (for version control and repeatability) I exported a tcl script from the quartus gui using the Project->generate tcl file for project menu item to use in my batch system.

I let both of these cores be "master" OCT so that each core has the OCT embedded in it.

I manually instantiated the rup and rdn pins and connected them to the rup and rdn pins that the nios core vhdl file brings out.

On to testing.