Using UniPHY leaving RUP and RDN unconnected for a DDR2 SDRAM controller

Part one of my theory looks to be confirmed (see below). What to do if a core brings out the pins in VHDL or Verilog?

From

http://www.altera.com/support/devices/io/features/io-features.html#onchiptermination

On-Chip Termination

When to Use

An OCT output pin provides on-chip impedance matching capability to a 25-ohm or 50-ohm trace to reduce reflections-induced noise on the signal.

Use OCT with calibration in Cyclone III FPGAs for higher calibration accuracy to account for temperature and voltage condition variations.

How to Use

In the Assignment Editor, from I/O standard assignments, select from a list of available OCT I/O standards. Valid choices are 25-ohm or 50-ohm termination type, at various VCCIO levels, and with a calibration option.

When using series OCT with calibration on a pin, the RUP pin and RDN pin in the same side bank where the target pin resides must be connected to an external resistor, and each tied to VCCIO and GND, respectively. Use a 25-ohm resistor for 25-ohm termination type, and a 50-ohm resistor for 50-ohm termination type.

When using series OCT without calibration, an external resistor to the RUP and RDN pins is not required. In that case, the RUP and RDN pins can be used as regular I/O.