Using UniPHY leaving RUP and RDN unconnected for a DDR2 SDRAM controller

This is also driving me crazy. I have a DDR3 core and a QDR core, both using UNIPHY, and created inside SOPC. Both cores bring out the rup,rdn pins in the VHDL ports of the Nios core,

but when I wire them up to the real pins I get the errors stating the pins are already busy.

I also see auto generated rup and rdn pins in the log files for these cores. Which one is it Quartus??

I "Think" what is going on is that I have constraints that set the pins to 50 Ohm termination. I'm testing a theory that this causes Quartus to generate the OCT hardware automagically which then interferes with the manually instantiated cores in SOPC.

I commented out the 50 Ohm settings in my constraints and am trying again.

Is this documented somewhere? OCT - auto vs manual instantiation?