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Frequent ContributorHi MFric2,
Perhaps you may consider to use NIOS II with Avalon Tri-State Conduit components in FPGA to access the CFI flash. The PFL can only be use with Quartus programmer via JTAG interface. You can refer to chapter 5.2.6. Nios II Processor Booting from CFI Flash in the Embedded Design handbook for the details:
We don't have the exact method that you are looking but you can try refer to the Cyclone V dev kit which has similar application. Please refer to the link below for the Cyclone V dev kit reference manual, schematic and BUP(board portal update) design as reference:
Most of the FPGA dev kit come with the BUP(board portal update) design that utilize NIOS II with Avalon Tri-State Conduit components in FPGA. While the PFL in CPLD is use to perform the FPPx16 configuration to Cyclone V.
You can refer to chapter "FPGA Programming from Flash Memory" for some explanation and Figure 2–4. PFL Configuration on the FPGA-CPLD-flash connection from the Cyclone V GT dev kit reference manual:
Regards,
Nooraini
