Altera_Forum
Honored Contributor
Honored ContributorUsing memory
Why inferred ram does not have a reset signal ?
thank you.Forum Discussion
10 Replies
Altera_ForumYour design should take care of initializing the data before using it ;-)
- Altera_Forum
The memory blocks internal to FPGA's do not typically have a clearing function that zeros the memory locations, but rather clear output registers that hold the last value read, or address latching registers for holding addresses, etc.
Refer to the sevtion fo the particular families data sheet for details on these clearing functions. As such, most inferred RAM do not see a need for the reset function. - Altera_Forum
Thank you for your answer about memory initilization.
Q: How forcing quartus to infer M4k RAM by using Tcl Language? Thank you? - Altera_Forum
Why not using the mega wizard manager ?
- Altera_Forum--- Quote Start --- Why not using the mega wizard manager ? --- Quote End --- because all my project design must be wrote in VHDL.
- Altera_Forum
And ..?
I'm also coding in VHDL, and the megawizard can generate vhdl file ! - Altera_Forum
Yes, the megawizard generates a vhdl file. But, in my design project I can not use a generated component because each ligne VHDL wrote must be justified.
So, a generated component has a supplementary code. In my design, I do not like to use the ALTERA labrary, too. - Altera_Forum
I'm with the same problem . . . i want to use the chip memory block without using a megafunction because i want portability .
Anyone knows how to do it ? - Altera_Forum
Hi,
Turn over 'Inferring Altera Megafunctions from HDL Code' section in quartus handbook and you will find all that you need. - Altera_Forum
Thanks!!!!!!!!
