Using DDR Ctrlr and PCIe Mgfnctn on PCI Express Development Kit Stratix II GX Edition

I'm encountering a very similar problem while modifying the SDRAM DDR2 reference design.

The documentation provided by Altera may be adequate for people familiar with the inner details of PCIe but being a PCIe newbie I'm finding it not very comprehensive. I'm more than willing to put in the effort but the gaps in the design walk-throughs don't help...besides replies from Altera support that the "reference design is not meant to be modified" doesn't really help! There is also no information provided on how the SIIGXPCIE.exe functions.

Having modified the reference design, I can write data to the SDRAM but when I read the data using the provided SIIGXPCIe.exe than the data is sometimes not in the order in which I write or doesn't appear to be at the address we specify. This gives the impression that the way we are handling addressing is incorrect. The modifications were made to get a better understanding of the reference design, and we simply replaced the data received from the Rx_Pcie with data from a counter. The burst length size was then hardcoded along with the address at which the data was intended to be written.

Would anyone have any idea on how we can control addressing such that we can write data to a specific address location? Also, any insight on what could be used from the PC-end to create an equivalent to the provided 'SIIGXPCIE.exe' would be most helpful.

Thanks in advance

Hitul