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Hi All,
I have questions about this designe example:
http://www.altera.com/support/examples/dsp-builder/exm-cic-decimation-filter.html I have attached the design files. In the file fir_compiler_v7_2.vhd, it goes
"number_of_input_channels" value="2"
"input_bit_width" value="16"
"output_bit_width" value="35"
So the two input channels of fir conveys 8-bit 'I' and 8-bit 'Q' data respectively (correct me if it is wrong). Does that mean 'I' and 'Q' are merged into 35-bit packet on the output interface so the first half contains 'I' and the second half has 'Q'?
Then the 35-bit output is sent to Avalon-ST Packet Format Converter. The converter seperates the 35-bit 'IQ' packet into two sources, 35-bit 'I' and 35-bit 'Q'. Does the converter perform the bit extension to add more bits to I and Q outputs, respectively, to have the bit width of 35?
Many Thanks,
Lee
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I would think that each of I and Q is 16 bits wide. The final result of each is 35 bits wide. I and Q results are interleaved at FIR output and dinterleaved by the converter.
Honored Contributor
