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jjang
New Contributor
New ContributorUsing Altera PLL make 500Khz or below
When i Using ALTPLL, i Usually make 500khz and below xx kHz Frequency Clock. @ 50Mhz / 100Mhz Input clock. But Cyclone 5, Different PLL IP Core. - ALTPLL → Altera PLL, so it doesn't support fo...
Hi,
just read PLL Intel FPGA IP messages thoroughly. It instructs you to enable physical output clock pararameters to configure cascaded output counters.
AqidAyman_Altera
Regular Contributor
Regular ContributorHi,
I wish to follow up on this issue. Have you able to use the cascading feature to generate the low frequencies output clock?
Regards,
Aqid
