UNIphy simulation confusion

Hi,

I want to simulate the UNIphy based DDR2 system. I have written a top file to control the DDR2 and I have tested it on the actual board and it works fine. Now, I need to simulate the design to include other logic modules in my system. I have written a basic testbench but I don't know where is the model for the memory and where should I place my testbench code etc. Please, briefly guide me about the next steps. I have run out of time so please send a reply at the earliest possible. Thanks in advance.

Regards,

Abdul Rehman.