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Honored Contributor
Honored ContributorUniphy DDR3 controller waitrequest simulation problem/How to simulate Uniphy memory
Hello everyone, I am trying to simulate the DDR3 Uniphy memory controller I have just created in Qsys(see screenshot) and I am running into the following problem: At the beginning, the wai...
Altera_ForumHonored Contributor
Honored ContributorTry generating the example design from the UniPHY IP Parameter Editor. This includes a traffic generator and a generic memory model based on the parameters you specify. If you want to simulate with the specific memory on your board, you can usually download a simulation model from the vendor of the memory and add it to your simulation testbench.
This training is a little old, but it does include steps and a demonstration about simulating the interface: https://www.altera.com/support/training/course/omem1110.html
