Forum Discussion
Deshi_Intel
Regular Contributor
6 years agoHi,
Can you check whether you had provided clock to pll_refclk pin and release the global_reset pin ?
Thanks.
Is this issue occurs on Intel FPGA dev kit board or your own board ?
Regards,
Deshi
DSold3
New Contributor
6 years agowhat do you mean by releasing the global_reset pin? Right now it is connected to the debug reset from the cpu and the clk reset pin.
I'm using Terasic DE4 530 University Program board.
Regards, Alberto.