Honored Contributor
Honored ContributorHi Jim,
Glad you found the problem! I never tried to reset the SOPC system since there were other blocks in there that needed to continue working even if there is no video input. I guess I could have made a separate reset for the CVI, but in the end I changed the way the video decoder was managed to ensure that the output clock never goes away. The problems I had wsa definitely related to interrupting the video clock. Interrupting the data is no problem. I never reaaly had time to go back and setup test cases to isolate the problem and to make it repeatable (does one ever have time?). I recently also discovered through simulation that if you use the clocked video output, but you do not supply it with a video clock, then writing to any of its registers locks up the Avalon bus - the CVO permanently asserts the wait_request line. There also seems to be some logic that runs off the video output clock and which depends on the clock being present. Again I feel they should have placed all logic in the SOPC clock domain and at the very last stage pass the data (and sync lines) through a dual clock FIFO. It just makes the system more robust. Good luck with your project! Niki
