Honored Contributor
Honored ContributorNiki,
The additional instance it what would fail to work. It appears that I have found the problem, though. Whereas I had the first channel's SD CVI set to synchronize to F1, the second channel had been overlooked and was set to synchronize to F0. Upon recompiling with both channels set to synchronize to F1, I have not since had trouble flowing data through the system. I'm not certain, but I would suppose having the CVI synchronize to F0 was resulting in an overflow as my datavalid line would not assert until my string recognizer saw a F0 SAV which was perhaps too late for the CVI to sync to and instead, it had to wait through the F1 frame for the next F0. What with all the problems that this one setting has caused me, I will be sure to keep in mind the data clock issue. Have you found that resetting the SOPC when the CVI enters invalid states is a valid means of handling this problem? I ask as removal of data without losing the entire system is the next issue with which I have to deal. Thank you very much for your help. -Jim
