UF-FFT, FFT IP Core, interpreting performance and resource utilization

Hi:

For your first question: This is the maximum clock rate they were able to achieve in the particular family. But remember they were only attempting to fit a single FFT in the design with minimal other hardware, so that may be optimistic. usually your clock rate is driven by your data sample rate, but that may or may not be the case.

If you are close to those numbers as far as your requirements, expect to spend lots of time in timing closure. But you should be able to do 160-200 MHz with no problem depending on the family.

If you need better than that you should look at the Stratix V or 10 family.

As far as size, yes your reasoning is correct, but you need to add what ever additional resources are required to mux/demux the data between the 10 cores as well.

This again are estimates from a single run. The size of the design in your logic may vary significantly depending on your timing constraints and your area/speed constraints in the synthesis tool.

Pete