Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

UDP for TSE MAC

Hi all,

Currently I am using TSE MAC, but is there any UDP Verilog module already available to connect with TSE MAC? I tried to search around but can not find one. Thanks a lot!

15 Replies

Show More
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    It looks fine indeed... Could you also attach your alt_sys_init.c ? Maybe something went wrong when it was generated.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Hi, Daixiwen, I also have another question about this example. I find that the packet format is different from the typical UDP packet. In this case, can we transfer data from the board to the PC via UDP? Also do we need to rewrite our own packet receive application code to get the data, rather than using "recvfrom()" socket? Thanks!

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    It seems that there is something wrong in your bsp generation... The acceleration components have this line in their *_sw_tcl file: 

    set_sw_property auto_initialize false
    and this should instruct the tools not to put the *_INIT macros in the alt_sys_init() function.

    What version of quartus/Nios do you use? I tried to compile the example with both 8.0 and 9.0SP2 (I don't have 10.0) and in both cases it created the alt_sys_init() without those macro calls. Did you do any change to the *_sw.tcl files in the components?

    As a temporary workaround you can comment those lines in alt_sys_init.c, but you,ll need to do that again each time it is regenerated: 

    void alt_sys_init( void )
{
    ALTERA_AVALON_TIMER_INIT( SYS_CLK_TIMER, sys_clk_timer );
    ALTERA_AVALON_TIMER_INIT( HIGHT_RES_TIMER, hight_res_timer );
    ALTERA_AVALON_TIMER_INIT( STAT_TIMER, stat_timer );
    ALTERA_AVALON_CFI_FLASH_INIT( EXT_FLASH, ext_flash );
    ALTERA_AVALON_JTAG_UART_INIT( JTAG_UART, jtag_uart );
    ALTERA_AVALON_SYSID_INIT( SYSID, sysid );
    TRIPLE_SPEED_ETHERNET_INIT( TSE_MAC, tse_mac );
    ALTERA_AVALON_SGDMA_INIT( SGDMA_TX, sgdma_tx );
    ALTERA_AVALON_SGDMA_INIT( SGDMA_RX, sgdma_rx );
/*
    PRBS_PACKET_GENERATOR_INIT( GENERATOR_0, generator_0 );
    PRBS_PACKET_GENERATOR_INIT( GENERATOR_1, generator_1 );
    PRBS_PACKET_GENERATOR_INIT( GENERATOR_2, generator_2 );
    PRBS_PACKET_GENERATOR_INIT( GENERATOR_3, generator_3 );
    UDP_PAYLOAD_INSERTER_INIT( UDP_INSERTER_0, udp_inserter_0 );
    UDP_PAYLOAD_INSERTER_INIT( UDP_INSERTER_1, udp_inserter_1 );
    UDP_PAYLOAD_INSERTER_INIT( UDP_INSERTER_2, udp_inserter_2 );
    UDP_PAYLOAD_INSERTER_INIT( UDP_INSERTER_3, udp_inserter_3 );
    ERROR_PACKET_DISCARD_INIT( ERROR_DISCARD, error_discard );
    UDP_PORT_TO_CHANNEL_MAPPER_INIT( UDP_MAPPER, udp_mapper );
    OVERFLOW_PACKET_DISCARD_INIT( OVERFLOW_DISCARD, overflow_discard );
    UDP_PAYLOAD_EXTRACTOR_INIT( EXTRACTOR_0, extractor_0 );
    UDP_PAYLOAD_EXTRACTOR_INIT( EXTRACTOR_1, extractor_1 );
    UDP_PAYLOAD_EXTRACTOR_INIT( EXTRACTOR_2, extractor_2 );
    UDP_PAYLOAD_EXTRACTOR_INIT( EXTRACTOR_3, extractor_3 );
    PRBS_PACKET_CHECKER_INIT( CHECKER_0, checker_0 );
    PRBS_PACKET_CHECKER_INIT( CHECKER_1, checker_1 );
    PRBS_PACKET_CHECKER_INIT( CHECKER_2, checker_2 );
    PRBS_PACKET_CHECKER_INIT( CHECKER_3, checker_3 );
*/
}

    As for your second questions, the packets generated or received by the hardware have the Ethernet, IP and UDP header in addition to the data, so this may be why they look different.

    In this system you can have both hardware and software handled packets. The idea is to handle the low bandwidth traffic in software (through the standard BSD sockets API, including recvfrom) and handle the high bandwidth traffic directly in hardware (through the acceleration components).
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    I did not change anything about *_sw.tcl files in the components, and I compiled the example in Quartus II 8.0. All the files in the acceleration components are used directly without any change. Now the situation is that such errors did not show up when compiling the example directly. However, I changed the device from Stratix II GX to Stratix III, and also changed the ddr2 dram configuration. Without any other changes, I compiled the project and still got the same errors. I don't understand the reason.