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Altera_Forum
Honored Contributor
Honored ContributorUART IP - input clock
Hello, I'm using a MAX10 FPGA and I'm trying to generate a UART IP core. During the generation process, after I select the buad rate, stop, parity bits, I get an error "the input clock frequen...
Altera_ForumHonored Contributor
Honored ContributorHi,
Refer below link https://www.altera.com/support/support-resources/knowledge-base/ip/2018/error--rs232_0--the-input-clock-frequency-must-be-known-at-gener.html Let me know if this has helped resolve the issue you are facing or if you need any further assistance. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)
