Forum Discussion
dtopou1
New Contributor
New ContributorUART Core IP (RS-232 Serial Port)
I am having issue with UART (RS-232 Serial Port) Intel FPGA IP v19.2.0 generation on Quartus pro 22.4. The the RX path dose not receive any data. Generated code for the core seams wrong in module "...
mabdrahi
Contributor
ContributorHi,
Yes, we can generate the uart from qsys.
I would like to suggest to you, using the GHRD(https://github.com/altera-opensource/ghrd-socfpga
) then generate the uart instantiate IP, porting over to top level. im not sure if you doing that already for your project.
dtopou1New Contributor
New ContributorIs generated code resembles the code that I have attached? If so can you take a look at the data RX path and in specific module "dproc_qsys_uart_0_altera_avalon_uart_1920_tpslhhy_rx_stimulus_source" and how we can remove "SIMULATION-ONLY CONTECTS" sections and replace it with the synthesis translation? I really do not want simulation only contents I need to simulate normal UART RX behavior!
