Forum Discussion
dtopou1
New Contributor
3 years agoUART Core IP (RS-232 Serial Port)
I am having issue with UART (RS-232 Serial Port) Intel FPGA IP v19.2.0 generation on Quartus pro 22.4. The the RX path dose not receive any data. Generated code for the core seams wrong in module "...
mabdrahi
Contributor
2 years agoHi,
I open your design and i saw error while opening the top file.
I would like to have a call with you to look more deeper
may i know when do you free?
what is your GMT, my GMT is +8.
- dtopou12 years ago
New Contributor
The example project is there to allow you to generate IP source code. The only think you need to do is to generate qsys. Then you can analyze the source code that it generated.