Honored Contributor
Honored Contributor> Do you have an idea what is the maximum clock we can use in the vip suite components?
There are some numbers on the user guide but they might not be very relevant since fMax will depend on the parameterization. The deinterlacer in high quality mode will most probably NOT run at 150MHz on CycloneIII. The frame buffer should just about make it. Other cores should be able to do more than that in general so it would be a bit surprising if you were having issues there. It is often necessary to use pipeline bridges on the Avalon-MM memory bus to get the SOPC Builder fabric to meet timing.
