Honored Contributor
Honored ContributorHi,
I am not an expert with timing closure related issues but you probably need to be more explicit regarding this negative timing slack if you want someone else to be able to help. What is the path with an issue? What are the nodes involved? The deinterlacer and the frame buffer come with a SDC file to declare false timing paths. This may be automatic now but in the past this file had to be included manually to the design. 150MHz on a Cyclone III might be a bit just with the VIP and probably unecessary unless you are working with 1080p resolutions. As primiano suggested, I would downclock the cores to 100Mhz if possible. The memory bus should be able to handle 150Mhz (?) so perhaps you can keep this as is.
