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Altera_Forum
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14 years ago

Tutorial: Using the USB-Blaster as an SOPC/Qsys Avalon-MM master

Hi all, I've put together a tutorial on how to use the Altera JTAG-to-Avalon-MM master and Altera Verification IP Avalon-MM BFM Master under both SOPC builder and Qsys. http://www.ovro.cal...
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Altera_Forum
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11 years ago

Hi Dave,

sorry for the bad image quality. I should have ckecked this. Now, I uploaded the screenshots in a zip archive. Hopefully the shots are untouched now by the forum system....

I only use one client at a time. I need that one client in order to access the GX FPGA on my board. I think, by looking at the console output of the server, the server is connected to that FPGA correctly and the awaits the client to connect. This is also functioning as expected (judging the server console output). For the console output, please refer to the screenshot that is now in the zip archive.

After that, I think, I have not many options to do something wrong. I just enter an address and a data value in the jtag_client.tcl GUI and press "write".

The server reflects the entered address and data correctly in its console but tells me that there is an error with that command.

I don't think that I have any hardware access, because I signal tap my system but see no avalon signals toggling while I try to send my command.

Nevertheless, I will try the debug mode and see if I can find the error myself.

My hardware (the GX FPGA) is just meant to be a co-processor for the SX FPGA. So it only has some xsvr lines as communication interface and JTAG. That is the reason why I would like to use this JTAG-To-Avalon-Master thing for board test and firmware debug. Later on, if everything works as expected in the final design, I just need the xsvr link in order to send commands and data to the GX FPGA via a custom phy xsvr link.

I'm pretty confident that my design is on the right path because I use the same avalon slave component in the SX FPGA that I also use in the GX FPGA. The only difference is that my avalon master in the SX ist the LWH2F Bridge of the HPS, while in the GX, my avalon master ist the JTAG bridge. In the SX FPGA I have no problems to access the component via avalon.

So basically the question right now is if you have an idea why the command that is formed in the jtag_client.tcl GUI ist invalid for the jtag_sever.tcl process?

Regards,

Maik