TSE wtih rgmii

Hi,

Has anyone successfully implemented tse megacore with rgmii mode?

I have a problem with using the megacore. When setting the PHY as a delayed mode, the core doesn't receive any frame at all. The rgmii receiver side ports, rx_clk, rgmii_in, rx_control are directly connected with the FPGA port.

When the rx_clock is inverted in the FPGA, it looks working well.

The core userguide(8.0) indicates that the core captures 1st data by negative edge and 2nd data by positive edge, which doesn't follow the rgmii spec. If it is true, it is natural that the core can receive data correctly with inverted rx_clock.

# P4-45 in v8.0 userguide

# The current implementation of the RGMII receive interface expects a zero- or negative-# delay rx_clk relative to the receive data (clock comes before the data).

The description above is changed in v8.1 userguide as follows, but there is no errata about this. So I wonder what is the correct implementation of this core.

# The current implementation of the RGMII receive interface expec#ts a positive-delay

# rx_clk relative to the receive data (clock comes before the data).

Thanks