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Honored Contributor
Honored ContributorTSE RGMII rxdv error
Hello, i am using altera tse ip core 10/100/1000. It works very well for link 10/100. Tx direction works as well for link 1000. Rx direction is not working properly. Signal rxdv has error flag ...
Altera_ForumHonored Contributor
Honored ContributorHello almemar,
Rx CLK delay is a feauture of PHY chip. I use Marwell 88E1111. There is register Extended PHY Specific Control Register (offset 20). This register contains bit RGMII Receive Timing Control (bit 7). This bit selects mode of Rx Clk Delay. When you write log. 1 to this bit then additional delay is created. Then it is necessary perform sw reset of PHY chip. There is another solution (it is possible to put PLL to RX Clk then it is possible create delay in a FPGA). I use this scope: testequipmentconnection.com/39969/Tektronix_MSO4034.php Cheers, Vaclav
