TSE MAC(10/100 Mbps) with Marvell 88E1111 PHY in MII mode

HI,

I think you get the clocking concept in the reverse order.

1. receive_clock_connection (ff_rx_clk) transmit_clock_connection (ff_tx_clk) is referring to FPGA core logic avalon ST interface clock that normally source from FPGA PLL or from external clock source
2. pcs_mac_rx_clock_connection (rx_clk), pcs_mac_tx_clock_connection (tx_clk). These are the clock that byright should be connected to external PHY chip.

You can refer to TSE user guide doc page 54 onwards, 4.1.13. Connecting MAC to External PHYs for the connection diagram.

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf

I also found one TSE reference design that you can checkout as reference

• https://rocketboards.org/foswiki/view/Projects/AlteraSoCTripleSpeedEthernetDesignExample

Thanks.

Regards,

dlim