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rt52's avatar
rt52
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

TSE IP core on MAX10 not working

I have a custom board with a MAX10 and 2 TI DP83869 PHYs that are meant to transfer ethernet data from one PHY to the other through the MAX10. However, I cannot seem to get data to appear from the i...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

If there is packet appear at the Avalon ST TX side, then you may perform a MAC loopback test, and determine if the packet can loopback to the Avalon ST RX side. If not, it could be something wrong in your design or clock system. Are you running at 1Gbps? What is the FIFO data width?

Just to confirm, if using TCL script, the statistic counter is update correctly?

Regards -SK


rt52's avatar
rt52
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Ok, I am working on getting the eth_gen and eth_mon modules in my project, I will try the loopback when I have finished.

1 Gbps is the desired speed, and I am configuring the mac registers for this. The fifo data width is 32bits.

Yes, when the design is on the dev board, and the stats_chk script is executed, I see the statistics counters incrementing when traffic is sent through, but nothing from my uart.