Occasional Contributor
Regular ContributorHi,
Assuming the UART update is correct. If you don’t see the TX statistics counter is increasing, it look like there is no data sending out from the TX interface. I would suggest you to capture the signal tap to confirm if this is true, and you might also need double check your system to confirm there is a proper clock connection.
Regards -SK
Occasional ContributorI broke open the pipeline latches that connect the 2 MACs and did a signal tap read on the avalon bus coming from RGMII, but still nothing on the uart. If this is the case, I would at least expect the error counters to update.
Yes, that was my next thing to check. I have multiple clocks feeding everything. The IP core and all of my logic (including mac register write, read and uart) are on 50Mhz, the FIFOs are running on 100Mhz, and the platform designer instantiations are running on a 125Mhz, with the RGMII tx on a shifted 125Mhz. Do you notice anything off with that?
