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rt52's avatar
rt52
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

TSE IP core on MAX10 not working

I have a custom board with a MAX10 and 2 TI DP83869 PHYs that are meant to transfer ethernet data from one PHY to the other through the MAX10. However, I cannot seem to get data to appear from the i...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

Assuming the UART update is correct. If you don’t see the TX statistics counter is increasing, it look like there is no data sending out from the TX interface. I would suggest you to capture the signal tap to confirm if this is true, and you might also need double check your system to confirm there is a proper clock connection.

Regards -SK


  • rt52's avatar
    rt52
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    I broke open the pipeline latches that connect the 2 MACs and did a signal tap read on the avalon bus coming from RGMII, but still nothing on the uart. If this is the case, I would at least expect the error counters to update.

    Yes, that was my next thing to check. I have multiple clocks feeding everything. The IP core and all of my logic (including mac register write, read and uart) are on 50Mhz, the FIFOs are running on 100Mhz, and the platform designer instantiations are running on a 125Mhz, with the RGMII tx on a shifted 125Mhz. Do you notice anything off with that?