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rt52's avatar
rt52
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

TSE IP core on MAX10 not working

I have a custom board with a MAX10 and 2 TI DP83869 PHYs that are meant to transfer ethernet data from one PHY to the other through the MAX10. However, I cannot seem to get data to appear from the i...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


You may refer to the following design example for MAX 10, it consist of the pattern generator for ethernet packet.

https://fpgacloud.intel.com/devstore/platform/18.0.0/Standard/max-10-single-port-triple-speed-ethernet-and-on-board-phy-chip-design-example/


It look like there is another problem in your system design with UART that unable to update the statistics register, but it work well in TCL scripts.

The UART is not working in both dev kit and custom board, If this is only the statistics register not update correctly, but other registers are okay. I would suggest you to double check your code, to ensure the address are assigned correctly, and double check if you turn on the “include statistics counters” from the TSE IP.


Regards -SK


  • rt52's avatar
    rt52
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Looking at the example design, I see other components in the platform designer that I don't have in mine, like eth_gen and eth_mon. I will see about adding those back in to get loopback going, thanks.

    Yes, I can read/write the registers that are read/writable, but the read only statistics counters don't update.

    The register address for the statistics counter are correct and match the datasheet and the "include statistics counter" option is checked in platform designer.