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rt52's avatar
rt52
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

TSE IP core on MAX10 not working

I have a custom board with a MAX10 and 2 TI DP83869 PHYs that are meant to transfer ethernet data from one PHY to the other through the MAX10. However, I cannot seem to get data to appear from the i...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

Thank you for the reply.

  1. Do you initial a pattern generator to transmit the data when perform the local loopback test (e.g Pattern Generator -> TX -> Local loopback -> RX)?
  2. Is the local loopback work well in dev kit, but not your custom board?
  3. When perform the local loopback test, did you check the TSE IP Avalon ST interface? Are there any activities (both TX and RX)?
  4. If you suspect this is external PHY issue, I would suggest you to contact the third party vendor to advice.

Regards -SK


rt52's avatar
rt52
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

1) I am not sure where to find the pattern generator. Would I have to make one myself or is there one I could use? I did not see anything in the datasheet regarding that.

2) I will have to try that, but if the packet generator is an issue, I would guess not.

3) So I interrupted the pipeline latch that connects one MAC to the other and viewed in signal tap and saw I had data coming out of of the first MAC, but I still did not see any status registers update from my UART module. Could you think of any reason why the status register would not update? I have them enabled in the platform designer instantiation.

4) I am in contact with the PHY manufacturer trying to tackle this issue from both sides

Thanks