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rt52's avatar
rt52
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

TSE IP core on MAX10 not working

I have a custom board with a MAX10 and 2 TI DP83869 PHYs that are meant to transfer ethernet data from one PHY to the other through the MAX10. However, I cannot seem to get data to appear from the i...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


1) Is the state machine that used to configure the MAC and PHY already validated by using Development kit before you port over to the new board?


2) To ruled out if this is FPGA or PHY not configure properly, you can perform the MAC Loopback test. See section 4.1.9 in the following user guide.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf


3) Do you follow the TI PHY datasheet to configure it via the MDIO interface?


Regards -SK


  • rt52's avatar
    rt52
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    1) Yes, I have successfully passed data using the dev board, although none of the statistics registers in UART updated, only when running stats_chk in the system console when running the tcl scripts.

    2) I set up local loopback by writing x803B to command config reg, but I still do not see any status registers changing.

    Also tested a form of PHY loopback test by directly connecting the RGMII rx signal to the RGMII tx signal in the MAX10 and using signal tap to verify that they were the same. So it looks like our PHY does

    3) I should have mentioned that the PHYs are programmed via hardware strapping for the correct modes, RGMII to copper and RGMII to 1000Base-X and most of the configuration is done by that. I am able to write to the PHY, for example to set the activity and data LED signals to the proper mode, but all other settings should be done via the strapping.