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Altera_Forum's avatar
Altera_Forum
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16 years ago

TSE IP - Enable multicast - HashEntries

Hi

Sorry if my question is silly I am new to FPGA world.

Using Triple Speed Ethernet DataPath reference design as my base design.

Using Stratix II GX PCI Express dev kit

Question

Enabled multicast using SOPC builder for TSE megacore function. Now I am not able to understand where and how do I set logic for multicast hash entries to filter packets on.

Any code samples, document pointers or any help would be appreciated.

Thanks for the help in advance.

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Pls Pls it would be great if some one can help ?

    Thanks in advance.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Thanks for the Quick reply.

    Where can I find the list of TSE command_config offset addresses to set Hash entries ...

    Thanks
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    The user guide I pointed you to has all info for the MAC. Table 4-9 beginning on page 4-29 shows the register addresses for the MAC. Specifically on page 4-34 the table indicates the HASH table is located at addresses 0x100-0x1FC.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Jake,

    Noticed that the IOWR macros in header file is IOWR_32DIRECT(base, (0x100 + offset), data). Could you pls let me know what offset should I pass in? Is it between 0 - FC?

    I attempted to pass offset number as well as the actual byte offset from base, somehow the IOWR does not update the hash entries. Could you please help?

    Thank you.

    Caridee
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    Jake,

    Noticed that the IOWR macros in header file is IOWR_32DIRECT(base, (0x100 + offset), data). Could you pls let me know what offset should I pass in? Is it between 0 - FC?

    I attempted to pass offset number as well as the actual byte offset from base, somehow the IOWR does not update the hash entries. Could you please help?

    Thank you.

    Caridee

    --- Quote End ---

    I met the same issue: IOWR does not update the hash entries.

    Could anybody help me to understand what is wrong?
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I'd check that IOWR_32DIRECT() doesn't multiply the offset by 4.

    It is actually much safer to define C structs that map hardware registers than to use offset constants.

    Unfortunatly that isn't the was Altera have defined things - but it can be done quite easily.

    Just make sure the accesses bypass the data cache.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Unfortunately, it doesn't matter, IOWR_32DIRECT() is used or not...

    I tried to use uncached pointers also. Result is the same: TSE hash table registers are not really updated.

    Note, that there is no such problem with other TSE registers: I succeessfully use and update mac0, mac1, phy_addr, command_config, all phy_regs, etc...

    I cannot find any information if hash table registers could be write-protected somehow...