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Altera_Forum
Honored Contributor
Honored ContributorTSE ff_rx_data problem
The data I actually sent to the board is : 0000 ff ff ff ff ff ff 00 1d 7d 75 c4 24 08 06 00 01 ........}u.$.... 0010 08 00 06 04 00 01 00 1d 7d 75 c4 24 c0 a8 01 07 ........}u.$.... ...
Altera_ForumHonored Contributor
Honored ContributorYou figured out the solution before I could answer ;)
The PHY uses auto-negotiation to find out the fastest speed it can use on the link. For some reason it decided that it can only go in 100Base-T. The TSE mode isn't automatically set according to the PHY mode, it is up to you to read the PHY status through the MDIO interface and configure the TSE in gigabit or 100/10 Mbit mode. The first two null bytes could come from the fact that you enabled the "Align packet headers to 32-bit boundaries (applicable to 32-bit FIFO only)" option when configuring the TSE core. When this option is enabled (and I think it is enabled by default) the core adds two 0 bytes, so that the header is 16 bytes long and the packet data is aligned on a 32-bit boundary. It makes life easier for the driver. I don't know why you have those bytes at the end... The checksum should be the last 4 bytes. Do you have any error reported? Can you have a look at the rx_err signal? Did you enable the internal CRC module in the TSE core?
