TSE (Ethernet) - Core does not transmit data on RGMII TX, rest works perfectly fine

We are experiencing this same issue, but still can't get the tx to work even after the following experiments:

1) with altddio for enet_gtx_clk and constraining the output timing for edge-aligned (configured internal-delay option of 88E1111 PHY)

1b) enabled the Programmable IOE Delay (D5 with value of 31) on the enet_gtx_clk, which according to the C5 datasheet should shift the clock from 0.5 ns (min) to 1.2 ns (max)

3) with altddio for enet_gtx_clk, but driven by the 90deg phase out of the same PLL that supplies the tx_clk to the tx_data/ctl

We are using the Arrow SoCKit with the Terasic HSMC Communications board. Has anyone gotten this combination to work? Terasic does not supply board layout files (and so we can't probe the RGMII test points, assuming they even exist).

As a last-ditch effort, I might try driving the enet_gtx_clk directly from the PLL 90deg and/or implementing our own RGMII interface, to add a facility loopback... Any other ideas?