TSE Avalon-MM interface reg_busy stuck at LL1

Hi,

Reg_busy is status output signal from TSE IP. You are right, it should go low eventually.

· Perhaps you want to review your TSE design connection and initialization process and your board clocking and reset condition again.

A good debug approach will be to compare your TSE design with below reference design to aid in debug process

· Generate TSE simulation example design from TSE IP directly. Then you can run modelsim simulation to learn more about the expected TSE IP signal behaviour

· Or you can also refer to below TSE hardware reference design as guideline

o https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an647.pdf

Thanks.

Regards,

dlim