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Altera_Forum
Honored Contributor
13 years agoHello,
Here is test code: /* These will gate the data checking near the end of main */ volatile alt_u8 tx_done = 0; volatile alt_u8 rx_done = 0; void tx_callback_function(void * context) { tx_done++; /* main will be polling for this value being 1 */ } void rx_callback_function(void * context) { rx_done++; /* main will be polling for this value being 1 */ } // Base configuration register unsigned int * mac_addr0 = (unsigned int *)(TSE_BASE + 0x00C); // mac0 unsigned int * mac_addr1 = (unsigned int *)(TSE_BASE + 0x010); // mac1 // mdio_addr0 register unsigned int * mac_phy_addr = (unsigned int *)(TSE_BASE + 0x03C); // Command configuration register unsigned int * mac_command_configure = (unsigned int *)(TSE_BASE + 0x008); // MDIO Space 0 (map to PHY device 0) unsigned int * mac_phy_reg_addr_base = (unsigned int *)(TSE_BASE + 0x200); // ( PHY = DP8384I ) // PHY basic mode control register unsigned int * mac_phy_reg_0 = (unsigned int *)(TSE_BASE + 0x200); // PHY mode status register unsigned int * mac_phy_reg_1 = (unsigned int *)(TSE_BASE + 0x200 + 1 * 4); // PHY status register unsigned int * mac_phy_reg_10 = (unsigned int *)(TSE_BASE + 0x200 + 10 * 4); // PHY control register unsigned int * mac_phy_reg_19 = (unsigned int *)(TSE_BASE + 0x200 + 19 * 4); char rx_buf[1800]; char tx_buf[1800]; void init_phy() { # define PHY_RESET 0x8000 # define PHY_AUTONEG_ENA 0x1000 long i; *mac_phy_addr = 0x01; // associate MAC with with PHY addr = 0x01 *mac_phy_reg_0 = *mac_phy_reg_0 | PHY_AUTONEG_ENA; # define AUTO_MDIX 0x8000 *mac_phy_reg_19 = *mac_phy_reg_19 | AUTO_MDIX; } void init_tse() { *mac_addr0 = 0x17231c00; // set MAC = *mac_addr1 = 0x0000cb4a; // 00-1c-23-17-4a-cb # define TX_ENA 0x00000001 # define RX_ENA 0x00000002 # define PROMIS_EN 0x00000010 # define PAD_EN 0x00000020 # define TX_ADDR_INS 0x00000200 # define SW_RESET 0x00002000 # define CTR_FRM_ENA 0x00800000 *mac_command_configure = *mac_command_configure | SW_RESET; // Reset while ( *mac_command_configure & SW_RESET ) // wait for reset complete alt_putstr("reset in progress\n"); *mac_command_configure = *mac_command_configure | PROMIS_EN; *mac_command_configure = *mac_command_configure | PAD_EN; *mac_command_configure = *mac_command_configure | TX_ADDR_INS; *mac_command_configure = *mac_command_configure | CTR_FRM_ENA; *mac_command_configure = *mac_command_configure | RX_ENA; *mac_command_configure = *mac_command_configure | TX_ENA; } int main() { int i; init_tse(); alt_printf("command_cfg register is %x\n", *mac_command_configure); init_phy(); for(i = 0; i < 10000000; i++); alt_printf("PHY mode status is %x\n", *mac_phy_reg_1); alt_printf("PHY status is %x\n", *mac_phy_reg_10); alt_printf("PHY control is %x\n", *mac_phy_reg_19); alt_sgdma_dev * pSink = alt_avalon_sgdma_open(SGDMA_RX_NAME); if(pSink == NULL) alt_putstr("open sink error!\n"); else alt_putstr("sink was opened\n"); alt_sgdma_dev * pSource = alt_avalon_sgdma_open(SGDMA_TX_NAME); if(pSource == NULL) alt_putstr("open source error!\n"); else alt_putstr("source was opened\n"); /************************************************************** * Register the ISRs that will get called when each (full) * * transfer completes * ************************************************************/ alt_avalon_sgdma_register_callback(pSource, &tx_callback_function, (ALTERA_AVALON_SGDMA_CONTROL_IE_GLOBAL_MSK | ALTERA_AVALON_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK), NULL); alt_avalon_sgdma_register_callback(pSink, &rx_callback_function, (ALTERA_AVALON_SGDMA_CONTROL_IE_GLOBAL_MSK | ALTERA_AVALON_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK), NULL); /**************************************************************/ alt_sgdma_descriptor sinkDesc, sourceDesc; alt_sgdma_descriptor nextSinkDesc, nextSourceDesc; nextSinkDesc.control = 0; nextSourceDesc.control = 0; alt_avalon_sgdma_construct_stream_to_mem_desc(&sinkDesc, &nextSinkDesc, (alt_u32 *)rx_buf, 100, 0); alt_avalon_sgdma_construct_mem_to_stream_desc(&sourceDesc, &nextSourceDesc, (alt_u32 *)tx_buf, 100, 0, 0, 0, 0); for(i = 0; i < 6; i ++) { tx_buf = 0xff;}
for(i = 6; i < 12; i ++)
{
tx_buf = 0x11; } tx_buf[12] = 0; tx_buf[13] = 100; while(1) { //alt_avalon_sgdma_do_async_transfer(pSource, &sourceDesc); alt_avalon_sgdma_do_sync_transfer(pSource, &sourceDesc); while(tx_done == 0) {} alt_putstr("The transmit SGDMA has completed\n"); tx_done = 0; } } As a result, I see only command_cfg register is 800233 PHY mode status is 7869 PHY status is 0 PHY control is 0 sink was opened source was opened and nothing is transmitted via tse. Is it important, tse or phy is inited earlier?