Triple Speed Ethernet

I don't know about the test bench, but until now the information I read in the user guide was correct.

You must be careful about one thing: the Avalon Memory Mapped interface uses native addressing, which means that the address bus selects an address in the 32-bit space. On the other hand the documentation describes the interface seen from the software side on a CPU that uses an 8-bit addressing. As a result you must shift the address seen in the documentation by two bits to get the real value you need to put on the address bus. As an example to access the TX Command Status Register, documented as address 0x0E8, you need to put 0x3A on the address bus.

The differences you see could come from there.