Triple-Speed Ethernet MegaCore Function user guide, ug_ethernet.pdf, figure 8.1 shows ff_tx_clk and ff_rx_clk at 110 MHz, but table 8.1 lists a recommended frequency of 100 MHz, which is right?

Hi,

In addition, the input clock frequency for ff_tx_clk and ff_rx_clk signals to meet 1G bandwidth & it depends on width of FIFO that used while configuration. If width of the FIFO is 32-bit then these signal should have input clock at least 100 MHz & if it is 8-bit , then it needs to be at least 125 MHz.

Regards,

Vicky