Forum Discussion

DBart1's avatar
DBart1
Icon for New Contributor rankNew Contributor
6 years ago

Triple Speed Ethernet MDIO constraint

I am trying to constrain the MDIO port using set_input_delay for the Altera TSE IP core. I am a bit confused because the PHY chip & IEEE spec show a max 300ns clock to out relative to the MDC clock. ...
DBart1's avatar
DBart1
Icon for New Contributor rankNew Contributor
6 years ago

dlim,

Thanks. So if the recommendation by Intel to false path the mdio port?

Thanks