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DBart1's avatar
DBart1
Icon for New Contributor rankNew Contributor
6 years ago

Triple Speed Ethernet MDIO constraint

I am trying to constrain the MDIO port using set_input_delay for the Altera TSE IP core. I am a bit confused because the PHY chip & IEEE spec show a max 300ns clock to out relative to the MDC clock. ...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

HI,

I find out more about MAG account support requirement. Apparently we still able to support MAG account customer as long as it doesn't involve design info exchange and limited to more FPGA general usage enquiry.

So, I guess it's fine to answer your TSE IP usage enquiry questions.

Intel TSE IP has clock divider setting called "host clock divisor" to lower down the MDIO bus operating frequency.

You can refer to below TSE user guide doc table 19 (page 27)

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf

Intel recommends that the division factor is defined such that the MDC frequency does not exceed 2.5 MHz. (< 3.33MHz or max 300ns spec requirement)

So, as long as you configure the MDC clk to be 2.5MHz then it's pretty safe and doesn't required additional timing constraint.

Thanks.

Regards,

dlim