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ssd00's avatar
ssd00
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6 years ago

Triple speed Ethernet IP core

I am using quartus 16.0 lite version

When am using TSE mac ip for my project, while compiling upto timequest timing analysis it was succesfull, SOF file is also created, but in EDA netlist writer am getting this below error.

Error (204012): Can't generate netlist output files because the file "F:/shandeep/PROJECTS/NPOL 4 CHANNEL/example design/max10tse_project/platform/qsys_top/synthesis/submodules/altera_tse_clk_cntl.v" is an OpenCore Plus time-limited file. Remove the unlicensed cores or obtain a license for those OpenCore Plus time-limited IP cores used in the design. The Altera Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Error (204012): Can't generate netlist output files because the file "F:/shandeep/PROJECTS/NPOL 4 CHANNEL/example design/max10tse_project/platform/qsys_top/synthesis/submodules/altera_tse_a_fifo_opt_1246.v" is an OpenCore Plus time-limited file. Remove the unlicensed cores or obtain a license for those OpenCore Plus time-limited IP cores used in the design. The Altera Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

is there a license required for triple speed ethernet

3 Replies

  • AR_A_Intel's avatar
    AR_A_Intel
    Icon for Super Contributor rankSuper Contributor
    6 years ago
    Hello Welcome to INTEL forum. This error can happen if you have enabled an EDA simulation tool in your Quartus project. Could help check on this, disable the EDA simulation tool in your project by opening the Settings dialog box from the Quartus II Assignments menu. Select the category EDA Tool Settings and the subcategory Simulation. On the Simulation page of the Settings dialog box, change the Tool name option to <None>.
    • ssd00's avatar
      ssd00
      Icon for New Contributor rankNew Contributor
      6 years ago

      Hello AAbd

      As suggested by u i disabled the EDA simulation tool to none the error does not appear. I would to like verify the ethernet design in a custom MAX10 (10M16SAU169I7) board but upon full compilation the tool does not generate .pof file required for flashing the device. Does this mean i need license for my Triple speed Ethernet core if yes can you tell me how to obtain a evaluation license