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ssd00's avatar
ssd00
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7 years ago

Triple speed Ethernet IP core

I am using quartus 16.0 lite version When am using TSE mac ip for my project, while compiling upto timequest timing analysis it was succesfull, SOF file is also created, but in EDA netlist writer ...
AR_A_Intel's avatar
AR_A_Intel
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7 years ago
Hello Welcome to INTEL forum. This error can happen if you have enabled an EDA simulation tool in your Quartus project. Could help check on this, disable the EDA simulation tool in your project by opening the Settings dialog box from the Quartus II Assignments menu. Select the category EDA Tool Settings and the subcategory Simulation. On the Simulation page of the Settings dialog box, change the Tool name option to <None>.
  • ssd00's avatar
    ssd00
    Icon for New Contributor rankNew Contributor
    7 years ago

    Hello AAbd

    As suggested by u i disabled the EDA simulation tool to none the error does not appear. I would to like verify the ethernet design in a custom MAX10 (10M16SAU169I7) board but upon full compilation the tool does not generate .pof file required for flashing the device. Does this mean i need license for my Triple speed Ethernet core if yes can you tell me how to obtain a evaluation license