Forum Discussion
Ahmed_H_Intel1
Frequent Contributor
6 years agoHi,
The 8s include the board startup time? can you confirm?
BTW the C10 GX simple socket server is no longer available which, can you please check again and share with me screenshots of the design?
Regards,
ESama
New Contributor
6 years agoHello
Thank you for your answer.
8s doesn't include the board startup time: it is the real delay needed to transfer 10 Mo (the data rate obtained is roughly 10 Mbps as compared to the 1 Gbps expected). This 8s delay is timed from both the client
side and from the fpga side.
Please, find the link below to get the whole project in a zip file.
https://we.tl/t-BKf45e16g4
As compared to the original exemple given with the cyclone 10 GX dev
kit, the only code modification is in the simple_socket_server.c between
the lines 314 and 321.
The project is suited for the Quartus pro 18.1.
Very best regards
Etienne
Le 15/01/2020 à 09:33, Intel Forums a écrit :