Tri-Speed Ethernet IP - accessing "Command_Config Register"

Hi,

If you look at TSE user guide doc (table 56, page 108), TSE MAC register Avalon bus interface is 32 bits width wide data bus.

May I know where do you see 16 bits Avalon bus on TSE IP ?

Thanks.

Regards,

dlim

That's the width of the Quartus generated HDL component.

Can it be because I have the core set to PCS only ?

HI,

Your understanding is correct.

MAC reg address width is 32 bits but PCS reg address width is only 16 bits.

You can refer to TSE user guide doc for the reg control detail.

• Chapter 5.1 - MAC config reg space
• Chapter 5.2 - PCS config reg space

For your case, you just need to refer to chapter 5.2.

Thanks.

Regards,

dlim

So if configure the core as "PCS Only" - the MAC registers are essentially inaccessible ?

HI,

If you configured TSE IP with "PCS function" only, of course MAC function access will be disable as we won't expect user to use TSE MAC function anymore since you didn't initiate MAC function in the first place, right ? :)

Thanks.

Regards,

dlim

Just making sure...

I was thinking that perhaps the MAC section has registers shared by the PCS function that must be configured as well.

I'm referring to section 5.3.2 ( page 103 ) of the user guide:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf

In my use case the core acts as an SGMII bridge - no MAC functionality if required.

So in my case only steps 1 & 2 are necessary ?

1.External PHY Initialization using MDIO

2.PCS Configuration Register Initialization

HI,

Correct. You only need to perform step 1 and step 2.

I presume you had your own MAC IP where you will initialize your MAC IP separately.

Thanks.

Regards,

dlim

HI,

I hope I have cleared your doubt in my earlier feedback.

For now, I am setting this case to closure.

Thanks.

Regards,

dlim