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Honored Contributor
Honored ContributorTransmitting frames with Triple-Speed Ethernet MegaCore over Ethernet/RGMII
Hello, I'm working with Quartus II, and had implemented the Triple-Speed Ethernet Megacore. I simulate my design with ModelSim Altera Starter Edition. My hardware is the BeMicro CV A9 with ...
Altera_ForumHonored Contributor
Honored ContributorYes IIRC means If I remember correctly, sorry ;)
From what I am seeing from your wave files you are sending the packets correctly. The strange thing is that tx_control stays asserted even after the packet seems to be completely transmitted. The only odd thing that I can find out is that you have no clock on rx_clk. I know from experience that the TSE needs its clocks from the [R][G]MII side in order to complete its software reset cycle correctly. It could be that it isn't completely reset because of the lack of rx_clk. As for your real circuit, it could be a good idea to use signaltap on the signals in and out of the TSE and check that everything is the same than in the simulation. (and remember, if you monitor tx_clk and rx_clk in signaltap, you need a sampling frequency that is at least double that of the signals you monitor).
