Transceiver reference lock issue

Hi Experts,

I use Arria 10 GX device for my designed board and use transceiver phy for interface.

I have built many production boards and some of them, approximately 10 to 15%, interface don't work.

I have done many analysis, then I found a symptom on the failed board, that rx_is_lockedtoref is always low from completion of configuration. Of course, rx_set_locktoref goes to High.

Regarding the fine boards, after completion of configuration, rx_set_locktoref goes to High immediately, and rx_is_lockedtoref goes to high immediately also.

And consequent process is different between the fine board and failed board. On the both of boards, rx_set_locketodata goes to High after detect Rx signal, after rx_std_signaldet goes to High, then fine board receives data correctly, but failed board get random variant data only.

I guess that rx_is_lockedtoref (CDR reference lock) failure causes such symptom, then I have been inquiring the transceiver phy user guide for Arria 10, but I still have not gotten enough information.

So I would like to ask some questions.

(1) When lock-to-reference works, which settings are necessary for lock? Reset? Reconfiguration? proper frequency value, i.e. using prescaler?

(2) For lock-to-ref, is it used clkusr?

(3) I think lock-to-ref uses PLL, is it correct? And if so, what is a PLL-source clock, two clock should be there, one of them is reference clock and what is another one? If no, what is lock-to-ref?

I have other observation also, then I write it to my response for avoiding confusion.

Thanks,

TerryU